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In one RDNA 2 review on a tech site I remember that it detailed infinity cache as being the same kind of SRAM that they use in their Threadrippers and Epycs. In one Moore's Law Is Dead video he stated that getting V-cache working on the Zen 3 refresh would be a big boost for RDNA 3's infinity cache.
This had me thinking, does the current infinity cache used in RX 6000 GPUs use conventional cache or already use V-cache? Would RDNA 3 after the Zen 3 refresh bring a multiplication to the infinity cache size in 2022 without heat issues? I know from the statement and die-shot of the Zen 3 refresh that V-cache on Zen 3 won't cause or at least significantly cause heat issues because the extra cache stacks on top of pre-existing cache instead of the cores which are the hot spots. But I do not know of the die layout for RDNA 2/3 so I do not know if this is feasible and planned.
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It's traditional SRAM cache, which takes up quite a bit of die space, so the benefits have to outweigh the cost (they do).
With RDNA3, there's a separate memory control die linking compute dies/dice, which we think will house a larger Infinity Cache, and may even have built-in copper connections for a future V-cache add-in too (like Zen 3 did). Again, there have to be real benefits to go that route. Keeping more data on-chip helps perf/watt.
MCD is perfect for V-cache since heat will primarily be generated by compute dies, however, packaging heights become uneven, so I still think stabilizing silicon will be used (unless V-cache z-height can be ground down).
ID: hfyyul1 -
AMD uses "V-cache" to specifically refer to stacking cache on top of a die. RDNA2 are monolithic dies, with no stacking.
ID: hfyf7c9Most importantly, would I be right to assume that cache on RDNA 2 is horizontal to the cores just like Zen/Intel rather than above/under it so V-cache won't theoretically cause heat issues in RDNA 3?
ID: hfyg6u8The cache is to the side of the cores. That does not mean V-cache will not cause heat issues.
ID: hfykk18The current rumours are there is an mcd with all the cache among other things and gcds with all the graphics stuff for the chiplet based parts (not all of them) for rdna3
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Could anyone else even imagine a world where AMD 3D-stacked cache onto a GPU and didn't tell everyone about it? Of course Infinity Cache is not V-Cache.
In one RDNA 2 review on a tech site I remember that it detailed infinity cache as being the same kind of SRAM that they use in their Threadrippers and Epycs.
A global "Graphics optimized" cache based on Zen L3 is what Infinity Cache is, that and its size.
ID: hfynkf6But v-cache is infinity cache.... infinity cache is about how the system acesses the cache across the die, and the one die and v-cache are both accessed the same way in fact the v-cache most likely just appears as expanded cache area all in one L3 instead of appearing as separate cache.
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The difference between "v-cache" and a "conventional cache" is that v-cache is not on the same die. Infinity cache is on the same die, so it's not v-cache.
A cache is an SRAM component. There are a few design parameters which affect the cache (such as line size and associativity) and there things like where the cache is positioned on the chip and how it connects, but I don't think there are different "cache technologies". (Disclaimer: I'm not an ASIC designer.)
ID: hfykrw9Cache is usually 6T SRAM aka 6 transistor static ram. However there are other many other cache technologies... Intels CPUs that had an L4 were eDRAM caches up to 128MB and they proved to boost IPC considerably but were taken off the market probably because they were gutting some of Intel's high margin server market because some companies were nabbing the high IPC CPUs for server tasks.
Several consoles in the past have used cache using eDRAM (Wii U, PSP, PS2, Xbox 360 etc...), also some high end IBM mainframes use it or some other similar technology.
"Infinity cache is on the same die, so it's not v-cache."
Your semantics are all wrong, v-cache *is* infinity cache, its just an expansion thereof that sits on top of the CPU die. It is notable that it is built on a different more logic dense node than the base CPU die is allowing it to have double the sram per unit area which is why there is 32MB on die +64MB stacked v-cache. The vcache is ultra tightly integrated to the normal sram and it is highly likely they share many of the same control signals as the base die sram... with potentially thousands of TSVs bonding them together (toms hardware estimates 23 thousand).
Basically you are just wrong enough to be slightly misleading... at least read up on wikipedia and wikichip on the topic before you mislead people. Also I actually am a computer engineer though more at the board implementation level than ASICs.
ID: hfzjox1This (Pointing up)
Infinity Cache refers to the pipeline using Infinity Fabric.
V-Cache refers to the stacking to add additional cache.
V-Cache is still using Infinity Fabric for the pipeline.
Thus V-Cache is still Infinity Cache.
ID: hfyoq52Yea, eDRAM has been used as cache, but I think that in this context we're talking about SRAM purely. Do you agree that both v-cache and "infinity cache" are SRAM caches?
v-cache is infinity cache
Far as I understand, V-cache is a name applied specifically to a layered cache. "Infinity cache" is a name specifically applied to the near-DRAM-interface cache in the Radeon 6000 family.
(I think it's been speculated that it's called "infinity cache" because the connection between the cache and the cores is over infinity fabric -- though of course "infinity fabric" is also a rather generic name -- presumably a serial bus, which would be fine for the less latency sensitive nature of a GPU.)
Basically you are just wrong enough to be slightly misleading
Exactly what I think about your reply. 🙂
Yes, good point about the eDRAM cache being a thing, even though I do think it's worth pointing out that all caches discussed here are SRAM.
But your claim that two trademarks which aren't real technical term, but have some context, are the same, seems completely off.
ID: hfyksujEDRAM
Embedded DRAM (eDRAM) is dynamic random-access memory (DRAM) integrated on the same die or multi-chip module (MCM) of an application-specific integrated circuit (ASIC) or microprocessor. eDRAM's cost-per-bit is higher when compared to equivalent standalone DRAM chips used as external memory, but the performance advantages of placing eDRAM onto the same chip as the processor outweigh the cost disadvantages in many applications. In performance and size, eDRAM is positioned between level 3 cache and conventional DRAM on the memory bus, and effectively functions as a level 4 cache, though architectural descriptions may not explicitly refer to it in those terms.
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ID: hg15hx7Intels CPUs that had an L4 were eDRAM caches up to 128MB and they proved to boost IPC considerably but were taken off the market probably because they were gutting some of Intel's high margin server market because some companies were nabbing the high IPC CPUs for server tasks.
Basically you are just wrong enough to be slightly misleading... at least read up on wikipedia and wikichip on the topic before you mislead people. Also I actually am a computer engineer though more at the board implementation level than ASICs.
Probably because they were gutting their server market margins? They had Broadwell Xeon's with EDRAM available for all. Anyone attempting to use the segmented desktop models without ECC for server tasks is asking for trouble.
ID: hfyle16The difference between "v-cache" and a "conventional cache" is that v-cache is not on the same die. Infinity cache is on the same die, so it's not v-cache
No it's not, the example they used for vcache was a 2 chiplet zen 3 part with an additional 64mb vcache on each ccd. Vcache (vertical cache) is stacked cache, i.e. on top of other things on the same die, infinity cache is not vcache because it's not stacked on top of the die
Like how crystallwell (the 5775c) used a 128mb l4 cache on a separate die, doesn't make it vcache because it's off die cache
ID: hfyqeihThanks. It's a worthwhile clarification.
It was just a point to explain why infinity cache and v-cache can't be the same thing. I agree that I could have explained it better.
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The actual silicon itself is not anything special, no. There are custom designs for it that will determine density and whatnot, but it's more or less typical L3-type SRAM.
But I do not know of the die layout for RDNA 2/3 so I do not know if this is feasible and planned.
We really dont have any sort of decent details on how RDNA3 is gonna be packaged. There's several different ways they could go about it. I would expect that there will be a large, shared L3 cache 'chiplet' that addresses both GPU tiles in Navi 31 and 32. For Navi 33, I really dont really have a good guess. They could still use a smaller stacked L3 chiplet for its single GPU chip, but they could also just add the L3 to the main die, as they do with RDNA2 GPU's. Both could make sense depending on factors that we're not really privy to.
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My previous reply was a little incomplete and could be misleading, as some pointed out, so I'll try again to address what I hope the main point of your question is.
There are a few die image of RDNA 2 products. Here's one for Navi 22. As you can see (and this is true for other RDNA 2 dies, too), Infinity Cache is at the edge of the die, near the RAM interface, unlike on the CPU chiplet, where the cache is a block in the middle. This isn't ideal for a extra cache layer, so my guess is that it won't be added to RDNA 2 chips.
Some RDNA 3 products are said to use a chiplet architecture, with a cache on the I/O chiplet. In such a case the cache isn't added as a layer, but it's on a different die. So it's not V-cache, but it could be "infinity cache" in the sense that it will connect to other chiplets over infinity fabric.
The short of it is, I think it's likely that there's not 3D V-cache in RDNA 3, but my guess is that AMD is looking into using layering for its GPUs, too, like for CPUs. We'll have to wait and see in what form this turns out.
ID: hfzlu0hThanks for the die-shot.
Compared to Zen 3, RDNA 2 has cache around the cores instead of cores around the cache so I theorise that V-cache on RDNA if they continue to use this layout in the future will have worse thermals than Zen 3 with V-cache.
ID: hg04irjI see no reason to theorise that they'd be using this layout with V-cache over cores.
Also, cache is different with CPU and GPU. With Infinity Cache on a GPU, the cache size is predetermined alongside the memory bandwidth and core count. It's a 3-way balance, which probably means that tacking on more cache by itself is unlikely to bring in the same benefits as for a CPU.
If V-cache appears anywhere in RDNA 3, I think it will be on the I/O die. It will make sense, for example, to have such a die with a certain amount of cache when using a single processing chiplet, and double the cache when using two processing chiplets. With the I/O die a cache could very well be a single large block, and V-cache will fit well over it.
引用元:https://www.reddit.com/r/Amd/comments/q4g6la/what_cache_technology_does_infinity_cache_use/
if they do this they will likely do the stacking and grounding of the memory die first before placing the other dies.